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Tolerating Soft Errors in Deep Learning Accelerators with Reliable On-Chip Memory Designs

Research article (2018 IEEE International Conference on Networking, Architecture and Storage (NAS), 2018) · cited 57× · AI/ML
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Tolerating Soft Errors in Deep Learning Accelerators with Reliable On-Chip Memory Designs

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Tolerating Soft Errors in Deep Learning Accelerators with Reliable On-Chip Memory Designs is a scholarly article[1].

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APA 4ort.xyz Knowledge Graph. (2026). Tolerating Soft Errors in Deep Learning Accelerators with Reliable On-Chip Memory Designs. Retrieved May 24, 2026, from https://4ort.xyz/entity/tolerating-soft-errors-in-deep-learning-accelerators-with-reliable-on-chip-memory-designs
MLA “Tolerating Soft Errors in Deep Learning Accelerators with Reliable On-Chip Memory Designs.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/tolerating-soft-errors-in-deep-learning-accelerators-with-reliable-on-chip-memory-designs.
BibTeX @misc{4ortxyz_tolerating-soft-errors-in-deep-learning-accelerators-with-reliable-on-chip-memory-designs_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Tolerating Soft Errors in Deep Learning Accelerators with Reliable On-Chip Memory Designs}}, year = {2026}, url = {https://4ort.xyz/entity/tolerating-soft-errors-in-deep-learning-accelerators-with-reliable-on-chip-memory-designs}, note = {Accessed: 2026-05-24}}
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