SweRV
first open RISC-V processing core design and series of its descendants
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SweRV
Summary
Key Facts
- SweRV's developer is recorded as Western Digital[1].
- SweRV's copyright license is recorded as Apache Software License 2.0[2].
- SweRV's programmed in is recorded as SystemVerilog[3].
- SweRV's subclass of is recorded as open hardware[4].
- SweRV's subclass of is recorded as semiconductor intellectual property core[5].
- SweRV's software version identifier is recorded as 1.2[6].
- SweRV's software version identifier is recorded as 1.5[7].
- SweRV's software version identifier is recorded as 1.6[8].
- SweRV's software version identifier is recorded as 1.7[9].
- SweRV's software version identifier is recorded as 1.8[10].
- SweRV's software version identifier is recorded as 1.9[11].
- SweRV's publication date is recorded as +2019-01-24T00:00:00Z[12].
- SweRV's source code repository URL is recorded as https://github.com/chipsalliance/Cores-SweRV[13].
- SweRV's copyright status is recorded as copyrighted[14].