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Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays

Research article (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023) · cited 32× · AI/ML
academia openalex:W4320712936
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Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays

Summary

Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays is a scholarly article[1].

Key Facts

  • Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays's instance of is recorded as scholarly article[2].

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Direct Wikidata claims

  1. [2] ↑ . wikidata.org.

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays. Retrieved May 24, 2026, from https://4ort.xyz/entity/sense-model-hardware-codesign-for-accelerating-sparse-cnns-on-systolic-arrays
MLA “Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/sense-model-hardware-codesign-for-accelerating-sparse-cnns-on-systolic-arrays.
BibTeX @misc{4ortxyz_sense-model-hardware-codesign-for-accelerating-sparse-cnns-on-systolic-arrays_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays}}, year = {2026}, url = {https://4ort.xyz/entity/sense-model-hardware-codesign-for-accelerating-sparse-cnns-on-systolic-arrays}, note = {Accessed: 2026-05-24}}
LLM prompt According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays — https://4ort.xyz/entity/sense-model-hardware-codesign-for-accelerating-sparse-cnns-on-systolic-arrays (retrieved 2026-05-24)

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