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Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format

Research article (IEEE Transactions on Circuits and Systems I Regular Papers, 2023) · cited 19× · AI/ML
academia openalex:W4385832149
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Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format

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Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format is a scholarly article[1].

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  • Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format's instance of is recorded as scholarly article[2].

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Nanning Zheng

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APA 4ort.xyz Knowledge Graph. (2026). Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format. Retrieved May 24, 2026, from https://4ort.xyz/entity/optimizing-fpga-based-dnn-accelerator-with-shared-exponential-floating-point-format
MLA “Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/optimizing-fpga-based-dnn-accelerator-with-shared-exponential-floating-point-format.
BibTeX @misc{4ortxyz_optimizing-fpga-based-dnn-accelerator-with-shared-exponential-floating-point-format_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format}}, year = {2026}, url = {https://4ort.xyz/entity/optimizing-fpga-based-dnn-accelerator-with-shared-exponential-floating-point-format}, note = {Accessed: 2026-05-24}}
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