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Optimizing FPGA-based Convolutional Encoder-Decoder Architecture for Semantic Segmentation

Research article (2019 IEEE 9th Annual International Conference on CYBER Technology in Automation, Control, and Intelligent Systems (CYBER), 2019) · cited 10× · AI/ML
academia openalex:W3016754202
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Optimizing FPGA-based Convolutional Encoder-Decoder Architecture for Semantic Segmentation

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Optimizing FPGA-based Convolutional Encoder-Decoder Architecture for Semantic Segmentation is a scholarly article[1].

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APA 4ort.xyz Knowledge Graph. (2026). Optimizing FPGA-based Convolutional Encoder-Decoder Architecture for Semantic Segmentation. Retrieved May 24, 2026, from https://4ort.xyz/entity/optimizing-fpga-based-convolutional-encoder-decoder-architecture-for-semantic-segmentation
MLA “Optimizing FPGA-based Convolutional Encoder-Decoder Architecture for Semantic Segmentation.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/optimizing-fpga-based-convolutional-encoder-decoder-architecture-for-semantic-segmentation.
BibTeX @misc{4ortxyz_optimizing-fpga-based-convolutional-encoder-decoder-architecture-for-semantic-segmentation_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Optimizing FPGA-based Convolutional Encoder-Decoder Architecture for Semantic Segmentation}}, year = {2026}, url = {https://4ort.xyz/entity/optimizing-fpga-based-convolutional-encoder-decoder-architecture-for-semantic-segmentation}, note = {Accessed: 2026-05-24}}
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