Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth Memory

Research article (2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2021) · cited 12× · AI/ML

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Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth Memory

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Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth Memory is a scholarly article^[1].

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Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth Memory's instance of is recorded as scholarly article^[2].

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Authored by 3

C. H. Jiang, David Ojika, Herman Lam

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C. H. Jiang, David Ojika, Herman Lam

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[2] ↑ Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth Memory — instance of (P31): scholarly article. wikidata.org.

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[1] ↑ Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth Memory is an instance of scholarly article (scholarly article) [P31, primary]. Wikidata. wikidata.org.

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4ort.xyz Knowledge Graph. (2026). Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth Memory. Retrieved May 24, 2026, from https://4ort.xyz/entity/optimized-fpga-based-deep-learning-accelerator-for-sparse-cnn-using-high-bandwidth-memory

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“Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth Memory.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/optimized-fpga-based-deep-learning-accelerator-for-sparse-cnn-using-high-bandwidth-memory.

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@misc{4ortxyz_optimized-fpga-based-deep-learning-accelerator-for-sparse-cnn-using-high-bandwidth-memory_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth Memory}}, year = {2026}, url = {https://4ort.xyz/entity/optimized-fpga-based-deep-learning-accelerator-for-sparse-cnn-using-high-bandwidth-memory}, note = {Accessed: 2026-05-24}}

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