Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic

Research article (2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021) · cited 10× · AI/ML

academia openalex:W3196072617

Press Enter · cited answer in seconds

Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic

Summary

Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic is a scholarly article^[1].

Key Facts

Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic's instance of is recorded as scholarly article^[2].

⭐ Popularity Graph

0/100 long tail

📊 Google Search Volume

no search data yet

Quick Facts

Instance of scholarly article

🔗 Connections

Authored by 1

Zhenjiang Dong

← Author of 1

Zhenjiang Dong

References

Programmatic citations — every numbered marker resolves to a verifiable graph row below.

Direct Wikidata claims

[2] ↑ Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic — instance of (P31): scholarly article. wikidata.org.

Class ancestry

[1] ↑ Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic is an instance of scholarly article (scholarly article) [P31, primary]. Wikidata. wikidata.org.

📑 Cite this page

Use these citations when quoting this entity in research, articles, AI prompts, or wherever provenance matters. We aggregate Wikidata + Wikipedia + authoritative open-data sources; the stitched, scored, cross-referenced view is what 4ort.xyz contributes.

APA

4ort.xyz Knowledge Graph. (2026). Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic. Retrieved May 24, 2026, from https://4ort.xyz/entity/low-bitwidth-cnn-accelerator-on-fpga-using-winograd-and-block-floating-point-arithmetic

MLA

“Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/low-bitwidth-cnn-accelerator-on-fpga-using-winograd-and-block-floating-point-arithmetic.

BibTeX

@misc{4ortxyz_low-bitwidth-cnn-accelerator-on-fpga-using-winograd-and-block-floating-point-arithmetic_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic}}, year = {2026}, url = {https://4ort.xyz/entity/low-bitwidth-cnn-accelerator-on-fpga-using-winograd-and-block-floating-point-arithmetic}, note = {Accessed: 2026-05-24}}

LLM prompt

According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic — https://4ort.xyz/entity/low-bitwidth-cnn-accelerator-on-fpga-using-winograd-and-block-floating-point-arithmetic (retrieved 2026-05-24)

Canonical URL: https://4ort.xyz/entity/low-bitwidth-cnn-accelerator-on-fpga-using-winograd-and-block-floating-point-arithmetic · Last refreshed: May 24, 2026