Latency-driven design for FPGA-based convolutional neural networks

Research article (2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017) · cited 90× · AI/ML

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Latency-driven design for FPGA-based convolutional neural networks

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Latency-driven design for FPGA-based convolutional neural networks is a scholarly article^[1].

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Latency-driven design for FPGA-based convolutional neural networks's instance of is recorded as scholarly article^[2].

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Authored by 2

Christos-Savvas Bouganis, Stylianos I. Venieris

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Christos-Savvas Bouganis, Stylianos I. Venieris

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[2] ↑ Latency-driven design for FPGA-based convolutional neural networks — instance of (P31): scholarly article. wikidata.org.

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[1] ↑ Latency-driven design for FPGA-based convolutional neural networks is an instance of scholarly article (scholarly article) [P31, primary]. Wikidata. wikidata.org.

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4ort.xyz Knowledge Graph. (2026). Latency-driven design for FPGA-based convolutional neural networks. Retrieved May 24, 2026, from https://4ort.xyz/entity/latency-driven-design-for-fpga-based-convolutional-neural-networks

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“Latency-driven design for FPGA-based convolutional neural networks.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/latency-driven-design-for-fpga-based-convolutional-neural-networks.

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@misc{4ortxyz_latency-driven-design-for-fpga-based-convolutional-neural-networks_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Latency-driven design for FPGA-based convolutional neural networks}}, year = {2026}, url = {https://4ort.xyz/entity/latency-driven-design-for-fpga-based-convolutional-neural-networks}, note = {Accessed: 2026-05-24}}

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According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): Latency-driven design for FPGA-based convolutional neural networks — https://4ort.xyz/entity/latency-driven-design-for-fpga-based-convolutional-neural-networks (retrieved 2026-05-24)

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