Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition

Research article (2016 IEEE International Electron Devices Meeting (IEDM), 2016) · cited 133× · AI/ML
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Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition

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Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition is a scholarly article[1].

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APA 4ort.xyz Knowledge Graph. (2026). Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition. Retrieved May 24, 2026, from https://4ort.xyz/entity/hyperdimensional-computing-with-3d-vrram-in-memory-kernels-device-architecture-co-design-for-energy-efficient-error-resi
MLA “Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/hyperdimensional-computing-with-3d-vrram-in-memory-kernels-device-architecture-co-design-for-energy-efficient-error-resi.
BibTeX @misc{4ortxyz_hyperdimensional-computing-with-3d-vrram-in-memory-kernels-device-architecture-co-design-for-energy-efficient-error-resi_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition}}, year = {2026}, url = {https://4ort.xyz/entity/hyperdimensional-computing-with-3d-vrram-in-memory-kernels-device-architecture-co-design-for-energy-efficient-error-resi}, note = {Accessed: 2026-05-24}}
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