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High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic

Research article (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019) · cited 156× · AI/ML
academia openalex:W2946355854
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High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic

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High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic is a scholarly article[1].

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APA 4ort.xyz Knowledge Graph. (2026). High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic. Retrieved May 24, 2026, from https://4ort.xyz/entity/high-performance-fpga-based-cnn-accelerator-with-block-floating-point-arithmetic
MLA “High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/high-performance-fpga-based-cnn-accelerator-with-block-floating-point-arithmetic.
BibTeX @misc{4ortxyz_high-performance-fpga-based-cnn-accelerator-with-block-floating-point-arithmetic_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic}}, year = {2026}, url = {https://4ort.xyz/entity/high-performance-fpga-based-cnn-accelerator-with-block-floating-point-arithmetic}, note = {Accessed: 2026-05-24}}
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