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Efficient Address Translation for Architectures with Multiple Page Sizes
Research article (Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017) · cited 97× · AI/ML
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APA4ort.xyz Knowledge Graph. (2026). Efficient Address Translation for Architectures with Multiple Page Sizes. Retrieved May 24, 2026, from https://4ort.xyz/entity/efficient-address-translation-for-architectures-with-multiple-page-sizes
MLA“Efficient Address Translation for Architectures with Multiple Page Sizes.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/efficient-address-translation-for-architectures-with-multiple-page-sizes.
BibTeX@misc{4ortxyz_efficient-address-translation-for-architectures-with-multiple-page-sizes_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Efficient Address Translation for Architectures with Multiple Page Sizes}}, year = {2026}, url = {https://4ort.xyz/entity/efficient-address-translation-for-architectures-with-multiple-page-sizes}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): Efficient Address Translation for Architectures with Multiple Page Sizes — https://4ort.xyz/entity/efficient-address-translation-for-architectures-with-multiple-page-sizes (retrieved 2026-05-24)
