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Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators

Research article (2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020) · cited 11× · AI/ML
academia openalex:W3047599609
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Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators

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Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators is a scholarly article[1].

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  • Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators's instance of is recorded as scholarly article[2].

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Direct Wikidata claims

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators. Retrieved May 24, 2026, from https://4ort.xyz/entity/bus-width-aware-off-chip-memory-access-minimization-for-cnn-accelerators
MLA “Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/bus-width-aware-off-chip-memory-access-minimization-for-cnn-accelerators.
BibTeX @misc{4ortxyz_bus-width-aware-off-chip-memory-access-minimization-for-cnn-accelerators_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators}}, year = {2026}, url = {https://4ort.xyz/entity/bus-width-aware-off-chip-memory-access-minimization-for-cnn-accelerators}, note = {Accessed: 2026-05-24}}
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