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Bit-width Adaptive Accelerator Design for Convolution Neural Network

Research article (2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018) · cited 14× · AI/ML
academia openalex:W2802200896
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Bit-width Adaptive Accelerator Design for Convolution Neural Network

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Bit-width Adaptive Accelerator Design for Convolution Neural Network is a scholarly article[1].

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APA 4ort.xyz Knowledge Graph. (2026). Bit-width Adaptive Accelerator Design for Convolution Neural Network. Retrieved May 24, 2026, from https://4ort.xyz/entity/bit-width-adaptive-accelerator-design-for-convolution-neural-network
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BibTeX @misc{4ortxyz_bit-width-adaptive-accelerator-design-for-convolution-neural-network_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Bit-width Adaptive Accelerator Design for Convolution Neural Network}}, year = {2026}, url = {https://4ort.xyz/entity/bit-width-adaptive-accelerator-design-for-convolution-neural-network}, note = {Accessed: 2026-05-24}}
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