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An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks

Research article (2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2015) · cited 34× · AI/ML
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An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks

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An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks is a scholarly article[1].

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  • An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks's instance of is recorded as scholarly article[2].

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APA 4ort.xyz Knowledge Graph. (2026). An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks. Retrieved May 24, 2026, from https://4ort.xyz/entity/an-energy-efficient-memory-based-high-throughput-vlsi-architecture-for-convolutional-networks
MLA “An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/an-energy-efficient-memory-based-high-throughput-vlsi-architecture-for-convolutional-networks.
BibTeX @misc{4ortxyz_an-energy-efficient-memory-based-high-throughput-vlsi-architecture-for-convolutional-networks_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks}}, year = {2026}, url = {https://4ort.xyz/entity/an-energy-efficient-memory-based-high-throughput-vlsi-architecture-for-convolutional-networks}, note = {Accessed: 2026-05-24}}
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