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An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture

Research article (IEEE Transactions on Computational Imaging, 2017) · cited 12× · AI/ML
academia openalex:W2587325968
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An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture

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An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture is a scholarly article[1].

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  • An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture's instance of is recorded as scholarly article[2].

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Direct Wikidata claims

  1. [2] ↑ . wikidata.org.

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture. Retrieved May 24, 2026, from https://4ort.xyz/entity/an-efficient-fpga-based-parallel-phase-unwrapping-hardware-architecture
MLA “An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/an-efficient-fpga-based-parallel-phase-unwrapping-hardware-architecture.
BibTeX @misc{4ortxyz_an-efficient-fpga-based-parallel-phase-unwrapping-hardware-architecture_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture}}, year = {2026}, url = {https://4ort.xyz/entity/an-efficient-fpga-based-parallel-phase-unwrapping-hardware-architecture}, note = {Accessed: 2026-05-24}}
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