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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training

Research article (2020 57th ACM/IEEE Design Automation Conference (DAC), 2020) · cited 37× · AI/ML
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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training

Summary

A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training is a scholarly article[1].

Key Facts

  • A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training's instance of is recorded as scholarly article[2].

Related Entities

Shimeng Yu

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Direct Wikidata claims

  1. [2] ↑ . wikidata.org.

Class ancestry

  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-two-way-sram-array-based-accelerator-for-deep-neural-network-on-chip-training
MLA “A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-two-way-sram-array-based-accelerator-for-deep-neural-network-on-chip-training.
BibTeX @misc{4ortxyz_a-two-way-sram-array-based-accelerator-for-deep-neural-network-on-chip-training_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training}}, year = {2026}, url = {https://4ort.xyz/entity/a-two-way-sram-array-based-accelerator-for-deep-neural-network-on-chip-training}, note = {Accessed: 2026-05-24}}
LLM prompt According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training — https://4ort.xyz/entity/a-two-way-sram-array-based-accelerator-for-deep-neural-network-on-chip-training (retrieved 2026-05-24)

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