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A Memory-Optimized and Energy-Efficient CNN Acceleration Architecture Based on FPGA

Research article (2019 IEEE 28th International Symposium on Industrial Electronics (ISIE), 2019) · cited 21× · AI/ML
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A Memory-Optimized and Energy-Efficient CNN Acceleration Architecture Based on FPGA

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A Memory-Optimized and Energy-Efficient CNN Acceleration Architecture Based on FPGA is a scholarly article[1].

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  • A Memory-Optimized and Energy-Efficient CNN Acceleration Architecture Based on FPGA's instance of is recorded as scholarly article[2].

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APA 4ort.xyz Knowledge Graph. (2026). A Memory-Optimized and Energy-Efficient CNN Acceleration Architecture Based on FPGA. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-memory-optimized-and-energy-efficient-cnn-acceleration-architecture-based-on-fpga
MLA “A Memory-Optimized and Energy-Efficient CNN Acceleration Architecture Based on FPGA.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-memory-optimized-and-energy-efficient-cnn-acceleration-architecture-based-on-fpga.
BibTeX @misc{4ortxyz_a-memory-optimized-and-energy-efficient-cnn-acceleration-architecture-based-on-fpga_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A Memory-Optimized and Energy-Efficient CNN Acceleration Architecture Based on FPGA}}, year = {2026}, url = {https://4ort.xyz/entity/a-memory-optimized-and-energy-efficient-cnn-acceleration-architecture-based-on-fpga}, note = {Accessed: 2026-05-24}}
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