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A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application

Research article (2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015) · cited 12× · AI/ML
academia openalex:W1830072322
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A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application

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A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application is a scholarly article[1].

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APA 4ort.xyz Knowledge Graph. (2026). A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-high-throughput-hevc-deblocking-filter-vlsi-architecture-for-8k-amp-x00d7-4k-application
MLA “A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-high-throughput-hevc-deblocking-filter-vlsi-architecture-for-8k-amp-x00d7-4k-application.
BibTeX @misc{4ortxyz_a-high-throughput-hevc-deblocking-filter-vlsi-architecture-for-8k-amp-x00d7-4k-application_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application}}, year = {2026}, url = {https://4ort.xyz/entity/a-high-throughput-hevc-deblocking-filter-vlsi-architecture-for-8k-amp-x00d7-4k-application}, note = {Accessed: 2026-05-24}}
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