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A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow

Research article (2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023) · cited 32× · AI/ML
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A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow

Summary

A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow is a scholarly article[1].

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  • A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow's instance of is recorded as scholarly article[2].

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Direct Wikidata claims

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-28nm-11-2tops-w-hardware-utilization-aware-neural-network-accelerator-with-dynamic-dataflow
MLA “A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-28nm-11-2tops-w-hardware-utilization-aware-neural-network-accelerator-with-dynamic-dataflow.
BibTeX @misc{4ortxyz_a-28nm-11-2tops-w-hardware-utilization-aware-neural-network-accelerator-with-dynamic-dataflow_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow}}, year = {2026}, url = {https://4ort.xyz/entity/a-28nm-11-2tops-w-hardware-utilization-aware-neural-network-accelerator-with-dynamic-dataflow}, note = {Accessed: 2026-05-24}}
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