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A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

Research article (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015) · cited 39× · AI/ML
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A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

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A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method is a scholarly article[1].

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  1. [2] ↑ . wikidata.org.

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-21-gbit-s-1-63-pj-bit-adaptive-ctle-and-one-tap-dfe-with-single-loop-spectrum-balancing-method
MLA “A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-21-gbit-s-1-63-pj-bit-adaptive-ctle-and-one-tap-dfe-with-single-loop-spectrum-balancing-method.
BibTeX @misc{4ortxyz_a-21-gbit-s-1-63-pj-bit-adaptive-ctle-and-one-tap-dfe-with-single-loop-spectrum-balancing-method_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method}}, year = {2026}, url = {https://4ort.xyz/entity/a-21-gbit-s-1-63-pj-bit-adaptive-ctle-and-one-tap-dfe-with-single-loop-spectrum-balancing-method}, note = {Accessed: 2026-05-24}}
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