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6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias

Research article (2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016) · cited 13× · AI/ML
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6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias

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6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias is a scholarly article[1].

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  • 6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias's instance of is recorded as scholarly article[2].

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Direct Wikidata claims

  1. [2] ↑ . wikidata.org.

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). 6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias. Retrieved May 24, 2026, from https://4ort.xyz/entity/6-8-a-1-5v-33mpixel-3d-stacked-cmos-image-sensor-with-negative-substrate-bias
MLA “6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/6-8-a-1-5v-33mpixel-3d-stacked-cmos-image-sensor-with-negative-substrate-bias.
BibTeX @misc{4ortxyz_6-8-a-1-5v-33mpixel-3d-stacked-cmos-image-sensor-with-negative-substrate-bias_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias}}, year = {2026}, url = {https://4ort.xyz/entity/6-8-a-1-5v-33mpixel-3d-stacked-cmos-image-sensor-with-negative-substrate-bias}, note = {Accessed: 2026-05-24}}
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