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Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing

Research article (2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2019) · cited 35× · AI/ML
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Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing

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Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing is a scholarly article[1].

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  • Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing's instance of is recorded as scholarly article[2].

Related Entities

Nuno Horta

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  1. [2] ↑ . wikidata.org.

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing. Retrieved May 24, 2026, from https://4ort.xyz/entity/using-polynomial-regression-and-artificial-neural-networks-for-reusable-analog-ic-sizing
MLA “Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/using-polynomial-regression-and-artificial-neural-networks-for-reusable-analog-ic-sizing.
BibTeX @misc{4ortxyz_using-polynomial-regression-and-artificial-neural-networks-for-reusable-analog-ic-sizing_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing}}, year = {2026}, url = {https://4ort.xyz/entity/using-polynomial-regression-and-artificial-neural-networks-for-reusable-analog-ic-sizing}, note = {Accessed: 2026-05-24}}
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