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The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems

Research article (IEEE Transactions on Circuits and Systems for Video Technology, 2016) · cited 23× · AI/ML
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The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems

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The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems is a scholarly article[1].

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  • The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems's instance of is recorded as scholarly article[2].

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Direct Wikidata claims

  1. [2] ↑ . wikidata.org.

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems. Retrieved May 24, 2026, from https://4ort.xyz/entity/the-vlsi-architecture-of-a-highly-efficient-deblocking-filter-for-hevc-systems
MLA “The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/the-vlsi-architecture-of-a-highly-efficient-deblocking-filter-for-hevc-systems.
BibTeX @misc{4ortxyz_the-vlsi-architecture-of-a-highly-efficient-deblocking-filter-for-hevc-systems_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems}}, year = {2026}, url = {https://4ort.xyz/entity/the-vlsi-architecture-of-a-highly-efficient-deblocking-filter-for-hevc-systems}, note = {Accessed: 2026-05-24}}
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