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Real‐Time H.265/HEVC Intra Encoding with a Configurable Architecture on FPGA Platform

Research article (Chinese Journal of Electronics, 2019) · cited 13× · AI/ML
academia openalex:W2976391544
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Real‐Time H.265/HEVC Intra Encoding with a Configurable Architecture on FPGA Platform

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Real‐Time H.265/HEVC Intra Encoding with a Configurable Architecture on FPGA Platform is a scholarly article[1].

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  • Real‐Time H.265/HEVC Intra Encoding with a Configurable Architecture on FPGA Platform's instance of is recorded as scholarly article[2].

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Direct Wikidata claims

  1. [2] ↑ . wikidata.org.

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). Real‐Time H.265/HEVC Intra Encoding with a Configurable Architecture on FPGA Platform. Retrieved May 24, 2026, from https://4ort.xyz/entity/realtime-h-265-hevc-intra-encoding-with-a-configurable-architecture-on-fpga-platform
MLA “Real‐Time H.265/HEVC Intra Encoding with a Configurable Architecture on FPGA Platform.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/realtime-h-265-hevc-intra-encoding-with-a-configurable-architecture-on-fpga-platform.
BibTeX @misc{4ortxyz_realtime-h-265-hevc-intra-encoding-with-a-configurable-architecture-on-fpga-platform_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Real‐Time H.265/HEVC Intra Encoding with a Configurable Architecture on FPGA Platform}}, year = {2026}, url = {https://4ort.xyz/entity/realtime-h-265-hevc-intra-encoding-with-a-configurable-architecture-on-fpga-platform}, note = {Accessed: 2026-05-24}}
LLM prompt According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): Real‐Time H.265/HEVC Intra Encoding with a Configurable Architecture on FPGA Platform — https://4ort.xyz/entity/realtime-h-265-hevc-intra-encoding-with-a-configurable-architecture-on-fpga-platform (retrieved 2026-05-24)

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