Generation of a Clocking Signal in Synchronized All-Digital PLL Networks

Research article (IEEE Transactions on Circuits & Systems II Express Briefs, 2018) · cited 11× · AI/ML

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Generation of a Clocking Signal in Synchronized All-Digital PLL Networks

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Generation of a Clocking Signal in Synchronized All-Digital PLL Networks is a scholarly article^[1].

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Generation of a Clocking Signal in Synchronized All-Digital PLL Networks's instance of is recorded as scholarly article^[2].

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Authored by 4

Dimitri Galayko, Elena Blokhina, Eugene Koskin, Orla Feely

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Dimitri Galayko, Elena Blokhina, Eugene Koskin, Orla Feely

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[2] ↑ Generation of a Clocking Signal in Synchronized All-Digital PLL Networks — instance of (P31): scholarly article. wikidata.org.

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[1] ↑ Generation of a Clocking Signal in Synchronized All-Digital PLL Networks is an instance of scholarly article (scholarly article) [P31, primary]. Wikidata. wikidata.org.

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@misc{4ortxyz_generation-of-a-clocking-signal-in-synchronized-all-digital-pll-networks_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Generation of a Clocking Signal in Synchronized All-Digital PLL Networks}}, year = {2026}, url = {https://4ort.xyz/entity/generation-of-a-clocking-signal-in-synchronized-all-digital-pll-networks}, note = {Accessed: 2026-05-24}}

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