Efficient Building Blocks for Hardware Neural Networks
2020 doctoral thesis by Adedamola Wuraola at University of Auckland
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Efficient Building Blocks for Hardware Neural Networks
Summary
Efficient Building Blocks for Hardware Neural Networks is a doctoral thesis[1].
Key Facts
- Efficient Building Blocks for Hardware Neural Networks authored Adedamola Wuraola[2].
- Efficient Building Blocks for Hardware Neural Networks's instance of is recorded as doctoral thesis[3].
- Efficient Building Blocks for Hardware Neural Networks's publisher is recorded as ResearchSpace@Auckland[4].
- Efficient Building Blocks for Hardware Neural Networks's copyright license is recorded as Creative Commons Attribution-NonCommercial-ShareAlike 3.0 New Zealand[5].
- Efficient Building Blocks for Hardware Neural Networks's country of origin is recorded as New Zealand[6].
- Efficient Building Blocks for Hardware Neural Networks's publication date is recorded as +2020-00-00T00:00:00Z[7].
- Efficient Building Blocks for Hardware Neural Networks's main subject is recorded as software engineering[8].
- Efficient Building Blocks for Hardware Neural Networks's work available at URL is recorded as https://researchspace.auckland.ac.nz/handle/2292/54777[9].
- Efficient Building Blocks for Hardware Neural Networks's Handle ID is recorded as 2292/54777[10].
- Efficient Building Blocks for Hardware Neural Networks's title is recorded as Efficient Building Blocks for Hardware Neural Networks[11].
- Efficient Building Blocks for Hardware Neural Networks's copyright holder is recorded as Adedamola Wuraola[12].
- Efficient Building Blocks for Hardware Neural Networks's thesis submitted to is recorded as University of Auckland[13].
- Efficient Building Blocks for Hardware Neural Networks's on focus list of Wikimedia project is recorded as NZThesisProject[14].
- Efficient Building Blocks for Hardware Neural Networks's copyright status is recorded as copyrighted[15].
- Efficient Building Blocks for Hardware Neural Networks's online access status is recorded as open access[16].
- Efficient Building Blocks for Hardware Neural Networks's thesis committee member is recorded as Sing Kiong Nguang[17].
- Efficient Building Blocks for Hardware Neural Networks's thesis committee member is recorded as Nitish D Patel[18].
Body
Designation and Status
Efficient Building Blocks for Hardware Neural Networks's instance of is recorded as doctoral thesis[3].