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Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning

Research article (IEEE Transactions on Multi-Scale Computing Systems, 2016) · cited 44× · AI/ML
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Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning

Summary

Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning is a scholarly article[1].

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  • Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning's instance of is recorded as scholarly article[2].

Related Entities

Shimeng Yu

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Direct Wikidata claims

  1. [2] ↑ . wikidata.org.

Class ancestry

  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning. Retrieved May 24, 2026, from https://4ort.xyz/entity/design-of-resistive-synaptic-array-for-implementing-on-chip-sparse-learning
MLA “Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/design-of-resistive-synaptic-array-for-implementing-on-chip-sparse-learning.
BibTeX @misc{4ortxyz_design-of-resistive-synaptic-array-for-implementing-on-chip-sparse-learning_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning}}, year = {2026}, url = {https://4ort.xyz/entity/design-of-resistive-synaptic-array-for-implementing-on-chip-sparse-learning}, note = {Accessed: 2026-05-24}}
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