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Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs

Research article (Proceedings of the 54th Annual Design Automation Conference 2017, 2017) · cited 415× · AI/ML
academia openalex:W2625954420
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Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs

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Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs is a scholarly article[1].

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APA 4ort.xyz Knowledge Graph. (2026). Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs. Retrieved May 24, 2026, from https://4ort.xyz/entity/automated-systolic-array-architecture-synthesis-for-high-throughput-cnn-inference-on-fpgas
MLA “Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/automated-systolic-array-architecture-synthesis-for-high-throughput-cnn-inference-on-fpgas.
BibTeX @misc{4ortxyz_automated-systolic-array-architecture-synthesis-for-high-throughput-cnn-inference-on-fpgas_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs}}, year = {2026}, url = {https://4ort.xyz/entity/automated-systolic-array-architecture-synthesis-for-high-throughput-cnn-inference-on-fpgas}, note = {Accessed: 2026-05-24}}
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