Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits

Summary

Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits is a doctoral thesis^[1].

Key Facts

• Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits authored A Technique for Optimizing Latency-constrained Circuits — author (P50): Soha Hassoun^[2].
• Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits's instance of is recorded as A Technique for Optimizing Latency-constrained Circuits — instance of (P31): doctoral thesis^[3].
• Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits's OCLC number is recorded as 40148264^[4].
• Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits's language of work or name is recorded as A Technique for Optimizing Latency-constrained Circuits — language of work or name (P407): English^[5].
• +1997-00-00T00:00:00Z marks the founding of Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits^[6].
• Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits's work available at URL is recorded as http://hdl.handle.net/1773/6916^[7].
• Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits's number of pages is recorded as {'unit': 'http://www.wikidata.org/entity/Q107256474', 'amount': '+154'}^[8].
• Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits's number of pages is recorded as {'unit': 'http://www.wikidata.org/entity/Q56761382', 'amount': '+9'}^[9].
• Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits's Handle ID is recorded as 1773/6916^[10].
• Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits's title is recorded as Architectural Retiming^[11].
• Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits's subtitle is recorded as A Technique for Optimizing Latency-constrained Circuits^[12].
• Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits's thesis submitted to is recorded as A Technique for Optimizing Latency-constrained Circuits — thesis submitted to (P4101): University of Washington^[13].
• Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits's on focus list of Wikimedia project is recorded as A Technique for Optimizing Latency-constrained Circuits — on focus list of Wikimedia project (P5008): WikiProject PCC Wikidata Pilot/University of Washington^[14].

Body

Designation and Status

Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits's instance of is recorded as A Technique for Optimizing Latency-constrained Circuits — instance of (P31): doctoral thesis^[3].

History and Context

+1997-00-00T00:00:00Z marks the founding of Architectural Retiming: A Technique for Optimizing Latency-constrained Circuits^[6].