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An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device

Research article (2022 IEEE International Symposium on Smart Electronic Systems (iSES), 2022) · cited 10× · AI/ML
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An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device

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An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device is a scholarly article[1].

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APA 4ort.xyz Knowledge Graph. (2026). An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device. Retrieved May 24, 2026, from https://4ort.xyz/entity/an-efficient-configurable-hardware-accelerator-design-for-cnn-on-low-memory-32-bit-edge-device
MLA “An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/an-efficient-configurable-hardware-accelerator-design-for-cnn-on-low-memory-32-bit-edge-device.
BibTeX @misc{4ortxyz_an-efficient-configurable-hardware-accelerator-design-for-cnn-on-low-memory-32-bit-edge-device_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device}}, year = {2026}, url = {https://4ort.xyz/entity/an-efficient-configurable-hardware-accelerator-design-for-cnn-on-low-memory-32-bit-edge-device}, note = {Accessed: 2026-05-24}}
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