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An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With <inline-formula> <tex-math notation="LaTeX">$0.175~\mu$ </tex-math> </inline-formula>W/Channel in 65-nm CMOS

Research article (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018) · cited 50× · AI/ML
academia openalex:W2900268635
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An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With <inline-formula> <tex-math notation="LaTeX">$0.175~\mu$ </tex-math> </inline-formula>W/Channel in 65-nm CMOS

Summary

An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With <inline-formula> <tex-math notation="LaTeX">$0.175~\mu$ </tex-math> </inline-formula>W/Channel in 65-nm CMOS is a scholarly article[1].

Key Facts

  • An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With <inline-formula> <tex-math notation="LaTeX">$0.175~\mu$ </tex-math> </inline-formula>W/Channel in 65-nm CMOS's instance of is recorded as scholarly article[2].

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Direct Wikidata claims

  1. [2] ↑ . wikidata.org.

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$0.175~\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;W/Channel in 65-nm CMOS. Retrieved May 24, 2026, from https://4ort.xyz/entity/an-area-efficient-128-channel-spike-sorting-processor-for-real-time-neural-recording-with-lt-inline-formula-gt-lt-tex-ma
MLA “An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$0.175~\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;W/Channel in 65-nm CMOS.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/an-area-efficient-128-channel-spike-sorting-processor-for-real-time-neural-recording-with-lt-inline-formula-gt-lt-tex-ma.
BibTeX @misc{4ortxyz_an-area-efficient-128-channel-spike-sorting-processor-for-real-time-neural-recording-with-lt-inline-formula-gt-lt-tex-ma_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$0.175~\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;W/Channel in 65-nm CMOS}}, year = {2026}, url = {https://4ort.xyz/entity/an-area-efficient-128-channel-spike-sorting-processor-for-real-time-neural-recording-with-lt-inline-formula-gt-lt-tex-ma}, note = {Accessed: 2026-05-24}}
LLM prompt According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$0.175~\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;W/Channel in 65-nm CMOS — https://4ort.xyz/entity/an-area-efficient-128-channel-spike-sorting-processor-for-real-time-neural-recording-with-lt-inline-formula-gt-lt-tex-ma (retrieved 2026-05-24)

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