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An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA

Research article (IEEE Transactions on Instrumentation and Measurement, 2017) · cited 44× · AI/ML
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An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA

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An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA is a scholarly article[1].

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  • An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA's instance of is recorded as scholarly article[2].

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA. Retrieved May 24, 2026, from https://4ort.xyz/entity/an-8-5-ps-two-stage-vernier-delay-line-loop-shrinking-time-to-digital-converter-in-130-nm-flash-fpga
MLA “An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/an-8-5-ps-two-stage-vernier-delay-line-loop-shrinking-time-to-digital-converter-in-130-nm-flash-fpga.
BibTeX @misc{4ortxyz_an-8-5-ps-two-stage-vernier-delay-line-loop-shrinking-time-to-digital-converter-in-130-nm-flash-fpga_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA}}, year = {2026}, url = {https://4ort.xyz/entity/an-8-5-ps-two-stage-vernier-delay-line-loop-shrinking-time-to-digital-converter-in-130-nm-flash-fpga}, note = {Accessed: 2026-05-24}}
LLM prompt According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA — https://4ort.xyz/entity/an-8-5-ps-two-stage-vernier-delay-line-loop-shrinking-time-to-digital-converter-in-130-nm-flash-fpga (retrieved 2026-05-24)

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