An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz
Summary
An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz is a scholarly article[1].
Key Facts
An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz's instance of is recorded as scholarly article[2].
References
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APA4ort.xyz Knowledge Graph. (2026). An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz. Retrieved May 24, 2026, from https://4ort.xyz/entity/an-18-bit-2ms-s-pipelined-sar-adc-utilizing-a-sampling-distortion-cancellation-circuit-with-107db-thd-at-100khz
MLA“An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/an-18-bit-2ms-s-pipelined-sar-adc-utilizing-a-sampling-distortion-cancellation-circuit-with-107db-thd-at-100khz.
BibTeX@misc{4ortxyz_an-18-bit-2ms-s-pipelined-sar-adc-utilizing-a-sampling-distortion-cancellation-circuit-with-107db-thd-at-100khz_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz}}, year = {2026}, url = {https://4ort.xyz/entity/an-18-bit-2ms-s-pipelined-sar-adc-utilizing-a-sampling-distortion-cancellation-circuit-with-107db-thd-at-100khz}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz — https://4ort.xyz/entity/an-18-bit-2ms-s-pipelined-sar-adc-utilizing-a-sampling-distortion-cancellation-circuit-with-107db-thd-at-100khz (retrieved 2026-05-24)
