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A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS

Research article (IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2018) · cited 14× · AI/ML
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A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS

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A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS is a scholarly article[1].

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APA 4ort.xyz Knowledge Graph. (2026). A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-spatial-multi-bit-sub-1-v-time-domain-matrix-multiplier-interface-for-approximate-computing-in-65-nm-cmos
MLA “A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-spatial-multi-bit-sub-1-v-time-domain-matrix-multiplier-interface-for-approximate-computing-in-65-nm-cmos.
BibTeX @misc{4ortxyz_a-spatial-multi-bit-sub-1-v-time-domain-matrix-multiplier-interface-for-approximate-computing-in-65-nm-cmos_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS}}, year = {2026}, url = {https://4ort.xyz/entity/a-spatial-multi-bit-sub-1-v-time-domain-matrix-multiplier-interface-for-approximate-computing-in-65-nm-cmos}, note = {Accessed: 2026-05-24}}
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