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A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical Capacitance Tomography Imaging Using Interframe Correlation

Research article (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017) · cited 26× · AI/ML
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A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical Capacitance Tomography Imaging Using Interframe Correlation

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A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical Capacitance Tomography Imaging Using Interframe Correlation is a scholarly article[1].

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APA 4ort.xyz Knowledge Graph. (2026). A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical Capacitance Tomography Imaging Using Interframe Correlation. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-pipelined-parallel-hardware-architecture-for-2-d-real-time-electrical-capacitance-tomography-imaging-using-interframe-
MLA “A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical Capacitance Tomography Imaging Using Interframe Correlation.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-pipelined-parallel-hardware-architecture-for-2-d-real-time-electrical-capacitance-tomography-imaging-using-interframe-.
BibTeX @misc{4ortxyz_a-pipelined-parallel-hardware-architecture-for-2-d-real-time-electrical-capacitance-tomography-imaging-using-interframe-_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical Capacitance Tomography Imaging Using Interframe Correlation}}, year = {2026}, url = {https://4ort.xyz/entity/a-pipelined-parallel-hardware-architecture-for-2-d-real-time-electrical-capacitance-tomography-imaging-using-interframe-}, note = {Accessed: 2026-05-24}}
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