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A novel low phase noise and low power DCO in 90 nm CMOS technology for ADPLL application

Research article (2016 24th Iranian Conference on Electrical Engineering (ICEE), 2016) · cited 12× · AI/ML
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A novel low phase noise and low power DCO in 90 nm CMOS technology for ADPLL application

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A novel low phase noise and low power DCO in 90 nm CMOS technology for ADPLL application is a scholarly article[1].

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  • A novel low phase noise and low power DCO in 90 nm CMOS technology for ADPLL application's instance of is recorded as scholarly article[2].

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Direct Wikidata claims

  1. [2] ↑ . wikidata.org.

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). A novel low phase noise and low power DCO in 90 nm CMOS technology for ADPLL application. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-novel-low-phase-noise-and-low-power-dco-in-90-nm-cmos-technology-for-adpll-application
MLA “A novel low phase noise and low power DCO in 90 nm CMOS technology for ADPLL application.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-novel-low-phase-noise-and-low-power-dco-in-90-nm-cmos-technology-for-adpll-application.
BibTeX @misc{4ortxyz_a-novel-low-phase-noise-and-low-power-dco-in-90-nm-cmos-technology-for-adpll-application_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A novel low phase noise and low power DCO in 90 nm CMOS technology for ADPLL application}}, year = {2026}, url = {https://4ort.xyz/entity/a-novel-low-phase-noise-and-low-power-dco-in-90-nm-cmos-technology-for-adpll-application}, note = {Accessed: 2026-05-24}}
LLM prompt According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A novel low phase noise and low power DCO in 90 nm CMOS technology for ADPLL application — https://4ort.xyz/entity/a-novel-low-phase-noise-and-low-power-dco-in-90-nm-cmos-technology-for-adpll-application (retrieved 2026-05-24)

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