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A Low-Power Hardware Architecture for On-Line Supervised Learning in Multi-Layer Spiking Neural Networks

Research article (2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018) · cited 20× · AI/ML
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A Low-Power Hardware Architecture for On-Line Supervised Learning in Multi-Layer Spiking Neural Networks

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A Low-Power Hardware Architecture for On-Line Supervised Learning in Multi-Layer Spiking Neural Networks is a scholarly article[1].

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APA 4ort.xyz Knowledge Graph. (2026). A Low-Power Hardware Architecture for On-Line Supervised Learning in Multi-Layer Spiking Neural Networks. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-low-power-hardware-architecture-for-on-line-supervised-learning-in-multi-layer-spiking-neural-networks
MLA “A Low-Power Hardware Architecture for On-Line Supervised Learning in Multi-Layer Spiking Neural Networks.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-low-power-hardware-architecture-for-on-line-supervised-learning-in-multi-layer-spiking-neural-networks.
BibTeX @misc{4ortxyz_a-low-power-hardware-architecture-for-on-line-supervised-learning-in-multi-layer-spiking-neural-networks_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A Low-Power Hardware Architecture for On-Line Supervised Learning in Multi-Layer Spiking Neural Networks}}, year = {2026}, url = {https://4ort.xyz/entity/a-low-power-hardware-architecture-for-on-line-supervised-learning-in-multi-layer-spiking-neural-networks}, note = {Accessed: 2026-05-24}}
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