Home › Entities › academia › A High-Performance Network-on-Chip Topology for Neuromorphic Architectures

A High-Performance Network-on-Chip Topology for Neuromorphic Architectures

Research article (22017 IEEE International Conference on Computational Science and Engineering (CSE) and IEEE International Conference on Embedded and Ubiquitous Computing (EUC), 2017) · cited 13× · AI/ML
academia openalex:W2742832966
Press Enter · cited answer in seconds

A High-Performance Network-on-Chip Topology for Neuromorphic Architectures

Summary

A High-Performance Network-on-Chip Topology for Neuromorphic Architectures is a scholarly article[1].

Key Facts

  • A High-Performance Network-on-Chip Topology for Neuromorphic Architectures's instance of is recorded as scholarly article[2].

References

Programmatic citations — every numbered marker resolves to a verifiable graph row below.

Direct Wikidata claims

  1. [2] ↑ . wikidata.org.

Class ancestry

  1. [1] ↑ . Wikidata. wikidata.org.

📑 Cite this page

Use these citations when quoting this entity in research, articles, AI prompts, or wherever provenance matters. We aggregate Wikidata + Wikipedia + authoritative open-data sources; the stitched, scored, cross-referenced view is what 4ort.xyz contributes.

APA 4ort.xyz Knowledge Graph. (2026). A High-Performance Network-on-Chip Topology for Neuromorphic Architectures. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-high-performance-network-on-chip-topology-for-neuromorphic-architectures
MLA “A High-Performance Network-on-Chip Topology for Neuromorphic Architectures.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-high-performance-network-on-chip-topology-for-neuromorphic-architectures.
BibTeX @misc{4ortxyz_a-high-performance-network-on-chip-topology-for-neuromorphic-architectures_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A High-Performance Network-on-Chip Topology for Neuromorphic Architectures}}, year = {2026}, url = {https://4ort.xyz/entity/a-high-performance-network-on-chip-topology-for-neuromorphic-architectures}, note = {Accessed: 2026-05-24}}
LLM prompt According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A High-Performance Network-on-Chip Topology for Neuromorphic Architectures — https://4ort.xyz/entity/a-high-performance-network-on-chip-topology-for-neuromorphic-architectures (retrieved 2026-05-24)

Canonical URL: https://4ort.xyz/entity/a-high-performance-network-on-chip-topology-for-neuromorphic-architectures · Last refreshed: