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A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor
Research article (2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018) · cited 15× · AI/ML
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor
Summary
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor is a scholarly article[1].
Key Facts
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor's instance of is recorded as scholarly article[2].
References
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Use these citations when quoting this entity in research, articles, AI prompts, or wherever provenance matters. We aggregate Wikidata + Wikipedia + authoritative open-data sources; the stitched, scored, cross-referenced view is what 4ort.xyz contributes.
APA4ort.xyz Knowledge Graph. (2026). A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-combined-all-digital-pll-buck-slack-regulation-system-with-autonomous-ccm-dcm-transition-control-and-82-average-voltag
MLA“A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-combined-all-digital-pll-buck-slack-regulation-system-with-autonomous-ccm-dcm-transition-control-and-82-average-voltag.
BibTeX@misc{4ortxyz_a-combined-all-digital-pll-buck-slack-regulation-system-with-autonomous-ccm-dcm-transition-control-and-82-average-voltag_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor}}, year = {2026}, url = {https://4ort.xyz/entity/a-combined-all-digital-pll-buck-slack-regulation-system-with-autonomous-ccm-dcm-transition-control-and-82-average-voltag}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor — https://4ort.xyz/entity/a-combined-all-digital-pll-buck-slack-regulation-system-with-autonomous-ccm-dcm-transition-control-and-82-average-voltag (retrieved 2026-05-24)
