Home ›
Entities
› academia
› A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors
Research article (2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018) · cited 242× · AI/ML
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors
Summary
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors is a scholarly article[1].
Key Facts
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors's instance of is recorded as scholarly article[2].
Use these citations when quoting this entity in research, articles, AI prompts, or wherever provenance matters. We aggregate Wikidata + Wikipedia + authoritative open-data sources; the stitched, scored, cross-referenced view is what 4ort.xyz contributes.
APA4ort.xyz Knowledge Graph. (2026). A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-65nm-4kb-algorithm-dependent-computing-in-memory-sram-unit-macro-with-2-3ns-and-55-8tops-w-fully-parallel-product-sum-
MLA“A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-65nm-4kb-algorithm-dependent-computing-in-memory-sram-unit-macro-with-2-3ns-and-55-8tops-w-fully-parallel-product-sum-.
BibTeX@misc{4ortxyz_a-65nm-4kb-algorithm-dependent-computing-in-memory-sram-unit-macro-with-2-3ns-and-55-8tops-w-fully-parallel-product-sum-_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors}}, year = {2026}, url = {https://4ort.xyz/entity/a-65nm-4kb-algorithm-dependent-computing-in-memory-sram-unit-macro-with-2-3ns-and-55-8tops-w-fully-parallel-product-sum-}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors — https://4ort.xyz/entity/a-65nm-4kb-algorithm-dependent-computing-in-memory-sram-unit-macro-with-2-3ns-and-55-8tops-w-fully-parallel-product-sum- (retrieved 2026-05-24)
