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A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction
Research article (IEEE Journal of Solid-State Circuits, 2022) · cited 21× · AI/ML
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction
Summary
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction is a scholarly article[1].
Key Facts
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction's instance of is recorded as scholarly article[2].
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Use these citations when quoting this entity in research, articles, AI prompts, or wherever provenance matters. We aggregate Wikidata + Wikipedia + authoritative open-data sources; the stitched, scored, cross-referenced view is what 4ort.xyz contributes.
APA4ort.xyz Knowledge Graph. (2026). A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-60-ms-s-5-mhz-bw-noise-shaping-sar-adc-with-integrated-input-buffer-achieving-84-2-db-sndr-and-97-3-db-sfdr-using-dyna
MLA“A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-60-ms-s-5-mhz-bw-noise-shaping-sar-adc-with-integrated-input-buffer-achieving-84-2-db-sndr-and-97-3-db-sfdr-using-dyna.
BibTeX@misc{4ortxyz_a-60-ms-s-5-mhz-bw-noise-shaping-sar-adc-with-integrated-input-buffer-achieving-84-2-db-sndr-and-97-3-db-sfdr-using-dyna_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction}}, year = {2026}, url = {https://4ort.xyz/entity/a-60-ms-s-5-mhz-bw-noise-shaping-sar-adc-with-integrated-input-buffer-achieving-84-2-db-sndr-and-97-3-db-sfdr-using-dyna}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction — https://4ort.xyz/entity/a-60-ms-s-5-mhz-bw-noise-shaping-sar-adc-with-integrated-input-buffer-achieving-84-2-db-sndr-and-97-3-db-sfdr-using-dyna (retrieved 2026-05-24)
