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A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA

Research article (Review of Scientific Instruments, 2019) · cited 11× · AI/ML
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A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA

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A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA is a scholarly article[1].

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  • A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA's instance of is recorded as scholarly article[2].

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  1. [2] ↑ . wikidata.org.

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-6-6-ps-rms-resolution-time-to-digital-converter-using-interleaved-sampling-method-in-a-28-nm-fpga
MLA “A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-6-6-ps-rms-resolution-time-to-digital-converter-using-interleaved-sampling-method-in-a-28-nm-fpga.
BibTeX @misc{4ortxyz_a-6-6-ps-rms-resolution-time-to-digital-converter-using-interleaved-sampling-method-in-a-28-nm-fpga_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA}}, year = {2026}, url = {https://4ort.xyz/entity/a-6-6-ps-rms-resolution-time-to-digital-converter-using-interleaved-sampling-method-in-a-28-nm-fpga}, note = {Accessed: 2026-05-24}}
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