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A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS
Research article (2019 Symposium on VLSI Circuits, 2019) · cited 98× · AI/ML
A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS
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A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS is a scholarly article[1].
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A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS's instance of is recorded as scholarly article[2].
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APA4ort.xyz Knowledge Graph. (2026). A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-5-1pj-neuron-127-3us-inference-rnn-based-speech-recognition-processor-using-16-computing-in-memory-sram-macros-in-65nm