A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply
Summary
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply is a scholarly article[1].
Key Facts
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply's instance of is recorded as scholarly article[2].
References
Programmatic citations — every numbered marker resolves to a verifiable graph row below.
Use these citations when quoting this entity in research, articles, AI prompts, or wherever provenance matters. We aggregate Wikidata + Wikipedia + authoritative open-data sources; the stitched, scored, cross-referenced view is what 4ort.xyz contributes.
APA4ort.xyz Knowledge Graph. (2026). A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-4ms-s-10b-sar-adc-with-integrated-class-a-buffers-in-65nm-cmos-with-near-rail-to-rail-input-using-a-single-1-2v-supply
MLA“A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-4ms-s-10b-sar-adc-with-integrated-class-a-buffers-in-65nm-cmos-with-near-rail-to-rail-input-using-a-single-1-2v-supply.
BibTeX@misc{4ortxyz_a-4ms-s-10b-sar-adc-with-integrated-class-a-buffers-in-65nm-cmos-with-near-rail-to-rail-input-using-a-single-1-2v-supply_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply}}, year = {2026}, url = {https://4ort.xyz/entity/a-4ms-s-10b-sar-adc-with-integrated-class-a-buffers-in-65nm-cmos-with-near-rail-to-rail-input-using-a-single-1-2v-supply}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply — https://4ort.xyz/entity/a-4ms-s-10b-sar-adc-with-integrated-class-a-buffers-in-65nm-cmos-with-near-rail-to-rail-input-using-a-single-1-2v-supply (retrieved 2026-05-24)
