A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory

Research article (2015 Symposium on VLSI Circuits (VLSI Circuits), 2015) · cited 20× · AI/ML
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A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory

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A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory is a scholarly article[1].

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  • A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory's instance of is recorded as scholarly article[2].

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APA 4ort.xyz Knowledge Graph. (2026). A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-23mw-face-recognition-accelerator-in-40nm-cmos-with-mostly-read-5t-memory
MLA “A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-23mw-face-recognition-accelerator-in-40nm-cmos-with-mostly-read-5t-memory.
BibTeX @misc{4ortxyz_a-23mw-face-recognition-accelerator-in-40nm-cmos-with-mostly-read-5t-memory_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory}}, year = {2026}, url = {https://4ort.xyz/entity/a-23mw-face-recognition-accelerator-in-40nm-cmos-with-mostly-read-5t-memory}, note = {Accessed: 2026-05-24}}
LLM prompt According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory — https://4ort.xyz/entity/a-23mw-face-recognition-accelerator-in-40nm-cmos-with-mostly-read-5t-memory (retrieved 2026-05-24)

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