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A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1<sup>st</sup>/2<sup>nd</sup>-Order DTC INL Calibration

Research article (2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023) · cited 10× · AI/ML
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A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration

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A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration is a scholarly article[1].

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  • A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration's instance of is recorded as scholarly article[2].

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  1. [2] ↑ . wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1<sup>st</sup>/2<sup>nd</sup>-Order DTC INL Calibration. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-10-to-300mhz-fractional-output-divider-with-80dbc-worst-case-fractional-spurs-using-auxiliary-pll-based-background-0th
MLA “A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1<sup>st</sup>/2<sup>nd</sup>-Order DTC INL Calibration.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-10-to-300mhz-fractional-output-divider-with-80dbc-worst-case-fractional-spurs-using-auxiliary-pll-based-background-0th.
BibTeX @misc{4ortxyz_a-10-to-300mhz-fractional-output-divider-with-80dbc-worst-case-fractional-spurs-using-auxiliary-pll-based-background-0th_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1<sup>st</sup>/2<sup>nd</sup>-Order DTC INL Calibration}}, year = {2026}, url = {https://4ort.xyz/entity/a-10-to-300mhz-fractional-output-divider-with-80dbc-worst-case-fractional-spurs-using-auxiliary-pll-based-background-0th}, note = {Accessed: 2026-05-24}}
LLM prompt According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1<sup>st</sup>/2<sup>nd</sup>-Order DTC INL Calibration — https://4ort.xyz/entity/a-10-to-300mhz-fractional-output-divider-with-80dbc-worst-case-fractional-spurs-using-auxiliary-pll-based-background-0th (retrieved 2026-05-24)

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