A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise

Research article (IEEE Journal of Solid-State Circuits, 2018) · cited 214× · AI/ML

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A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise

Summary

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise is a scholarly article^[1].

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A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise's instance of is recorded as scholarly article^[2].

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Direct Wikidata claims

[2] ↑ A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise — instance of (P31): scholarly article. wikidata.org.

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[1] ↑ A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise is an instance of scholarly article (scholarly article) [P31, primary]. Wikidata. wikidata.org.

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@misc{4ortxyz_a-1-2-v-dynamic-bias-latch-type-comparator-in-65-nm-cmos-with-0-4-mv-input-noise_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise}}, year = {2026}, url = {https://4ort.xyz/entity/a-1-2-v-dynamic-bias-latch-type-comparator-in-65-nm-cmos-with-0-4-mv-input-noise}, note = {Accessed: 2026-05-24}}

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According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise — https://4ort.xyz/entity/a-1-2-v-dynamic-bias-latch-type-comparator-in-65-nm-cmos-with-0-4-mv-input-noise (retrieved 2026-05-24)

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