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A 1.041-Mb/mm<sup>2</sup> 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications
Research article (2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022) · cited 130× · AI/ML
A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications
Summary
A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications is a scholarly article[1].
Key Facts
A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications's instance of is recorded as scholarly article[2].
Use these citations when quoting this entity in research, articles, AI prompts, or wherever provenance matters. We aggregate Wikidata + Wikipedia + authoritative open-data sources; the stitched, scored, cross-referenced view is what 4ort.xyz contributes.
APA4ort.xyz Knowledge Graph. (2026). A 1.041-Mb/mm<sup>2</sup> 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-1-041-mb-mm-sup-2-sup-27-38-tops-w-signed-int8-dynamic-logic-based-adc-less-sram-compute-in-memory-macro-in-28nm-with-
MLA“A 1.041-Mb/mm<sup>2</sup> 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-1-041-mb-mm-sup-2-sup-27-38-tops-w-signed-int8-dynamic-logic-based-adc-less-sram-compute-in-memory-macro-in-28nm-with-.
BibTeX@misc{4ortxyz_a-1-041-mb-mm-sup-2-sup-27-38-tops-w-signed-int8-dynamic-logic-based-adc-less-sram-compute-in-memory-macro-in-28nm-with-_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A 1.041-Mb/mm<sup>2</sup> 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications}}, year = {2026}, url = {https://4ort.xyz/entity/a-1-041-mb-mm-sup-2-sup-27-38-tops-w-signed-int8-dynamic-logic-based-adc-less-sram-compute-in-memory-macro-in-28nm-with-}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A 1.041-Mb/mm<sup>2</sup> 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications — https://4ort.xyz/entity/a-1-041-mb-mm-sup-2-sup-27-38-tops-w-signed-int8-dynamic-logic-based-adc-less-sram-compute-in-memory-macro-in-28nm-with- (retrieved 2026-05-24)
