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A 0.096-mm$^{2}~1$ –20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration
Research article (IEEE Transactions on Microwave Theory and Techniques, 2019) · cited 111× · AI/ML
A 0.096-mm$^{2}~1$ –20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration
Summary
A 0.096-mm$^{2}~1$ –20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration is a scholarly article[1].
Key Facts
A 0.096-mm$^{2}~1$ –20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration's instance of is recorded as scholarly article[2].
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APA4ort.xyz Knowledge Graph. (2026). A 0.096-mm$^{2}~1$ –20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-0-096-mm-2-1-20-ghz-triple-path-noise-canceling-common-gate-common-source-lna-with-dual-complementary-pmosnmos-configu