4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

Research article (2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023) · cited 34× · AI/ML

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4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

Summary

4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology is a scholarly article^[1].

Key Facts

4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology's instance of is recorded as scholarly article^[2].

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Direct Wikidata claims

[2] ↑ 4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology — instance of (P31): scholarly article. wikidata.org.

Class ancestry

[1] ↑ 4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology is an instance of scholarly article (scholarly article) [P31, primary]. Wikidata. wikidata.org.

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@misc{4ortxyz_4-5-a-9-25ghz-digital-pll-with-fractional-spur-cancellation-based-on-a-multi-dtc-topology_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology}}, year = {2026}, url = {https://4ort.xyz/entity/4-5-a-9-25ghz-digital-pll-with-fractional-spur-cancellation-based-on-a-multi-dtc-topology}, note = {Accessed: 2026-05-24}}

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